INDUSTRY

PATENTS

PUBLICATIONS

PRESENTATIONS

2003-on__
2000-2002
1997-1999
1995-1996
1990-1994
1973-1989

129. N. Nedovic, V. G. Oklobdzija, W. W. Walker, "A Clock Skew Absorbing Flip-Flop", 2003 IEEE International Solid-State Circuits Conference Digest of Technical papers, San Francisco, February 2003.
     


130. A. A. Farooqui, V. G. Oklobdzija, S. M. Sait, "Area-Time Optimal Adder with Relative Placement Generator", International Symposium on Circuits and Systems, Bangkok, Thailand, May 25-28, 2003.
     


131. X. Y. Yu, V. G. Oklobdzija, W. W. Walker, "An Efficient Transistor Optimizer for Custom Circuits", International Symposium on Circuits and Systems, Bangkok, Thailand, May 25-28, 2003.
     


132. B. R. Zeydel, V.G. Oklobdzija, S. Mathew, R.K. Krishnamurthy, S. Borkar, "A 90nm 1GHz 22mW 16x16-bit 2's Complement Multiplier for Wireless Baseband", Proceedings of the 2003 Symposium on VLSI Circuits, Kyoto, JAPAN, June 12 - 14, 2003.
     


133. V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy, "Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders", Proceedings of the International Symposium on Computer Arithmetic, ARITH-16, Santiago de Compostela, SPAIN, June 15-18, 2003.
     


134. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Minimization Method for Optimal Energy-Delay Extraction", Proceedings of the European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, PORTUGAL, September 16-18, 2003.
     


135. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Optimization of High-Performance Circuits", Proceedings of the 13th International Workshop on Power And Timing Modeling, Optimization and Simulation, Torino, Italy, September 10-12, 2003.
     


136. V. G. Oklobdzija, "Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment", IBM Journal of Research and Development, Vol. 47, No. 5/6, pp. 567-584, September/November 2003.
     


137. V. G. Oklobdzija, "Multi-GHz Systems Clocking", Invited Paper, Proceedings of the 5th International Conference on ASIC, Beijing, P.R. China, October 22-24, 2003.
     


138. V. G. Oklobdzija, "Issues in System on the Chip Clocking", Invited Paper, Proceedings of the IEEK System on Chip Design Conference, Seoul, Korea, November 5-6, 2003.
     


139. M. Vratonjic, B. R. Zeydel, H. Q. Dao, V. G. Oklobdzija, "Low-Power Aspects of Different Adder Topologies", 37th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 9-12, 2003.
     


140. N. Nedovic, W. W. Walker, V. G. Oklobdzija, "A Test Circuit for Measurement of Clocked Storage Element Characteristics", IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, pp. 1294-1304, August 2004.
     


141. H. Q. Dao, B. R. Zeydel, V. Zyuban, V. G. Oklobdzija, "A Method for Energy Optimization of Digital Pipelined Systems", The Fourth Annual IBM Austin Conference on Energy-Efficient Design, ACEED 2005, Austin, Texas, March 1-3, 2005.
     


142. N. Nedovic, V. G. Oklobdzija, "Dual-Edge Triggered Storage Elements and Clocking Strategy for Low-Power Systems", IEEE Transaction on VLSI Systems, Volume 13, Issue 5, pp. 577-590, May 2005.
     


143. V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy, "Comparison of High-Performance VLSI Adders in Energy-Delay Space", IEEE Transaction on VLSI Systems, Volume 13, Issue 6, pp. 754-758, June 2005.
     


144. B.R. Zeydel, T.T.J.H. Kluter, V. G. Oklobdzija, "Efficient Energy-Delay Mapping of Addition Recurrence Algorithms in CMOS", International Symposium on Computer Arithmetic, ARITH-17, Cape Cod, Massachusetts, USA, June 27-29, 2005.
     


145. M. Aleksic, N. Nedovic, K. W. Current, V. G. Oklobdzija, "A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers", in Proc. of the 15th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Leuven, Belgium, September 21-23, 2005.
     


146. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Architectural Considerations for Energy Efficiency", Proceedings of the International Conference on Computer Design, ICCD 2005, San Jose, California, October 2-5, 2005.
     


147. M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija, "Low- and Ultra Low-Power Arithmetic Units: Design and Comparison", Proceedings of the International Conference on Computer Design, ICCD 2005, San Jose, California, October 2-5, 2005.
     


148. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy-Efficient Optimization of the Viterbi ACS Unit Architecture", Proceedings of the Asian Solid-State Circuit Conference, A-SSCC 2005, Hsinchu, Taiwan, November 1-3, 2005.
     


149. S. K. Hsu, S. K. Mathew, M. A. Anders, B. R. Zeydel, V. G. Oklobdzija, R. K. Krishnamurthy, S. Y. Borkar, "A 110 GOPS/W 16-bit Multiplier and Reconfigurable PLA Loop in 90-nm CMOS", IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 256-264, January 2006.
     


150. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply Scaling", IEEE Transaction on VLSI Systems,Vol. 14, Issue 2, Feb. 2006 pp. 122-134.
     


151. C. Giacomotto, N. Nedovic, V. G. Oklobdzija, "Energy-Delay Space Analysis for Clocked Storage Elements under Process Variations", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 13-15, 2006.
     


152. B. R. Zeydel, V. G. Oklobdzija, "Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 13-15, 2006.
     


153. M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija, "Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 13-15, 2006.
     


154. X. Y. Yu, R. Montoye, K. Nowka, B. Zeydel, V. Oklobdzija, "Circuit Design Style for Energy Efficiency: LSDL and Compound Domino", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 13-15, 2006.
     


155. C. Giacomotto, N. Nikola, V. Oklobdzija, "The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements", IEEE Journal of Solid-State Circuits, Vol. 42, No. 6, pp. 1392-1404, June 2007.