INDUSTRY

PATENTS

PUBLICATIONS

PRESENTATIONS

2003-on__
2000-2002
1997-1999
1995-1996
1990-1994
1973-1989

47. V. G. Oklobdzija and D. Villeger, "Improving Multiplier Design By Using Improved Column Compression Tree And Optimized Final Adder In CMOS Technology", IEEE Transactions on VLSI Systems, Vol. 3, No. 2, June, 1995, 10 pages.
    


48. V. G. Oklobdzija, "Computer Organization: Architecture", The Engineering Handbook, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., 1995, 20 pages.
    


49. M. N. Dorojevets and V. G. Oklobdzija, "Multithreaded Decoupled Architecture", International Journal of High-Speed Computing, World Scientific Publisher, 16 pages, June, 1995.
    


50. V. G. Oklobdzija, D. Villeger, and S. S. Liu, "A Method For Speed Optimized Partial Product Reduction And Generation Of Fast Parallel Multipliers Using An Algorithmic Approach", IEEE Transactions on Computers, Vol. 45, No. 3, March 1996.
    


51. K. J. Runge, P. Lee, J. Correa, R.T. Scalettar, V.G. Oklobdzija, "Monte Carlo and Molecular Dynamic Simulations Using P4", Proceedings of the 9th Int'l Parallel Processing Symposium, Santa Barbara, California, April 24-29, 1995, 7 pages.
    


52. D. Maksimovic, V.G. Oklobdzija, "Integrated Power Clock Generators for Low Energy Logic", Proceedings of the 1995 Power Electronics Specialists Conference, Atlanta, Georgia, June 18-22, 1995.
    


53. V. G. Oklobdzija and B. Duchene, "Pass-Transistor Dual Value Logic For Low-Power CMOS", Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
    


54. C. Martel, V. G. Oklobdzija, R. Ravi and P. Stelling, "Design Strategies For Optimal Multiplier Circuits", Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, ENGLAND, July 19-21,1995, 8 pages.
    


55. V. G. Oklobdzija, "Computers", The Engineering Handbook, R. C. Dorf (Ed.), Introduction into Computers, a Chapter, CRC Press, Inc., 1995, 20 pages.
    


56. V. G. Oklobdzija, "An ECL Gate with Improved Speed And Low-Power in BiCMOS Process", Journal of Solid State Circuits, January 1996.
    


57. V. G. Oklobdzija and B. Duchene, "Logic Synthesis For Pass-Transistor Design", IEEE International Conference on Solid-State and Integrated-Circuit Technology, October 24-28, 1995, Beijing, China.
    


58. V. G. Oklobdzija and B. Duchene, "Pass-Transistor Logic Family for High-Speed and Low Power CMOS", Sixth International Symposium on IC Technology, Systems and Applications, ISIC-95, Singapore, September 6-8, 1995.
    


59. D. Maksimovic, V. G. Oklobdzija, "Clocked CMOS Adiabatic Logic with Single AC Power Supply", 21st European Solid-State Circuits Conference, September 19-21, 1995, Lille, FRANCE.
    


60. V. G. Oklobdzija, "Digital Systems", The Engineering Handbook, R. C. Dorf (Ed.), Introduction into Digital Systems, Chapter, in press, CRC Press, Inc., 1995.
    


61. V. G. Oklobdzija and B. Duchene, "Development and Synthesis Method for Pass-Transistor Logic Family for High-Speed and Low Power CMOS", 38th Midwest Symposium on Circuits and Systems, Rio de Janeriro, BRASIL, Auguts 13-16, 1995.
    


62. K. J. Runge, P. Lee, J. Correa, R. T. Seabettar, and V. G. Oklobdzija, "Simulations of Interacting Many Body Systems Using P4", Journal of High-Speed Computing, World Scientific Publisher, 27 pages, August 1995.
    


63. P. Bonatto, V. G. Oklobdzija, "Evaluation of Booth's Algorithm for Implementation in Parallel Multipliers", Twenty-Ninth Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29 - November 1, 1995.
    


64. Jean Noel, V. G. Oklobdzija, "New Pipelined Architecture for DSP", Twenty-Ninth Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29 - November 1, 1995.
    


65. V. G. Oklobdzija, P. Stelling, "Design Strategies for the Final Adder in a Parallel Multiplier", Twenty-Ninth Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29 - November 1, 1995.
    


66. V. G. Oklobdzija, "A Method for Generation of Fast Parallel Multipliers", 2nd International Conference on Massively Parallel Computing Systems, May 6-9, 1996, Ischia, ITALY.
    


67. K. W. Current, V. G. Oklobdzija, D. Maksimovic, "Low-Energy Logic Circuit Techniques for Multiple Valued Logic", Second Int'l Symposium on Multiple-Valued Logic, Santiago de Compostela, Spain, May 29-31, 1996.
    


68. P. Stelling , V. G. Oklobdzija, "Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier", special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol. 14, No. 3, December 1996.
    


69. R.H. Strandberg, J-C Le Duc, L.G. Bustamante, V. G. Oklobdzija, M. Soderstrand, "Efficient Realization of Squaring Circuit and Reciprocal used in Adaptive Sample Rate Notch Filters", special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol. 14, No. 3, December 1996.