INDUSTRY

PATENTS

PUBLICATIONS

PRESENTATIONS

2003-on__
2002-____
2000-2001
1996-1999
1994-1995
1990-1993
1982-1989

151. 2003 OPTIMIZING HIGH-PERFORMANCE DIGITAL CIRCUITS IN ENERGY CONSTRAINED ENVIRONMENT, Invited Presentation, 4^eme journes d'etudes Faible Tension Faible Consummation, FTFC'2003, Cercle National des Armees, Paris, FRANCE, May 15, 2003.
     


152. 2003 DESIGN OF POWER EFFICIENT VLSI ARITHMETIC: SPEED AND POWER TRADE-OFFS: Part-I, Part-II, Invited Tutorial, 16^th IEEE Symposium on Computer Arithmetic, Santiago de Compostela, SPAIN, June 15-18, 2003.
     


153. 2003 OPTIMZING HIGH-PERFORMANCE DIGITAL CIRCUITS IN ENERGY CONSTRAINED ENVIRONMENT, Instituto de Informatica, Grupo de Arquitectura de Computadores, Escuela Tecnica Superior Ingenieria, Universidad de Santiago de Compostela, Santiago de Compostela, SPAIN, June 20, 2003.
     


154. 2003 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS (part-I, part-II), IEEE Distinguished Lecture, Microelectronic Systems Laboratory, Institute of Microelectronics and Microsystems, Switzerland (West) Chapter of IEEE Solid-State Circuits Society, Swiss Federal Institute of Technology, Lausanne, SWITZERLAND, June 23, 2003.
     


155. 2003 DESIGN OF HIGH-PERFORMANCE ENERGY-EFFICIENT VLSI ARITHMETIC UNITS, Bart Zeydel, Invited Talk, Computer Engineering Department, Technical University of Delft, Delft, Netherlands, October 2, 2003.
     


156. 2003 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS, Samsung LSI Research Laboratories, Seoul, KOREA, September 5, 2003.
     


157. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, IEEE Distinguished Lectures Series, Korea IEEE Solid-State Circuits Chapter, Korea University, Seoul, KOREA, September 17, 2003.
     


158. 2003 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS, Center for Embedded Systems, Seoul National University, Seoul, KOREA, October 7, 2003.
     


159. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, IEEE Distinguished Lecture, China IEEE Solid-State Circuits Chapter, Beijing Branch, Institute of Microelectronics, Tsinghua University, Beijing, P.R. CHINA, October 20, 2003.
     


160. 2003 FUTURE DIRECTIONS IN CLOCKING MULTI-GHZ SYSTEMS, Microprocessor R&D Center, Department of Computer Science, Peking University, Beijing, P.R. CHINA, October 22, 2003.
     


161. 2003 BALANCING BETWEEN DESIGN AND DESIGN AUTOMATION, Invited, Panel Discussion Presentation, 5^th International Conference on ASIC, Beijing, P.R. China, October 23, 2003.
     


162. 2003 MULTI GHZ SYSTEM CLOCKING, Invited Presentation, 5^th International Conference on ASIC, Beijing, P.R. China, October 24, 2003.
     


163. 2003 POWER EFFICIENT VLSI ARITHMETIC: SPEED AND POWER TRADE-OFFS, IEEE Seoul Solid-State Circuits Chapter Distinguished Lecture, School of Electrical and Electronic Engineering, Yonsei University, Seoul, KOREA, October 31, 2003.
     


164. 2003 ENERGY MINIMIZATION METHOD FOR OPTIMAL ENERGY-DELAY, Fujitsu Research Laboratories, Kawasaki, JAPAN, December 3, 2003.
     


165. 2003 CLOCKED STORAGE ELEMENTS IN HIGH-PERFORMANCE AND LOW-POWER PROCESSORS, Hitachi Research Laboratories, Kokubunji, JAPAN, December 5, 2003.
     


166. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, IEEE Distinguished Lecture, Fudan University, Shanghai, P.R. CHINA, December 25, 2003.
     


167. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, Institute of VLSI Design, Zhejiang University, Hangzhou, P.R. CHINA, December 26, 2003.
     


168. 2004 POWER EFFICIENT VLSI ARITHMETIC, Departamento de Technologia Electronica, Universidad de Sevilla, Sevilla, SPAIN, May 6, 2004.
     


169. 2004 CLOCKING MULTI-GHZ SYSTEMS, Departamento de Technologia Electronica, Universidad de Sevilla, Sevilla, SPAIN, May 7, 2004.
     


170. 2004 ENERGY-DELAY RELATIONSHIP IN DIGITAL CIRCUITS DESIGN, Invited presentation, 24^th IEEE Internacional Conference on Microelectronics, Nis, SERBIA, May 18, 2004.
     


171. 2004 POWER EFFICIENT DESIGN: SPEED AND POWER TRADE-OFFS, Laboratoire de l'Informatique du Parallélisme, Ecole Normale Superieure de Lyon, Lyon, FRANCE, June 17, 2004.
     


172. 2004 ENERGY MINIMIZATION METHOD FOR OPTIMAL ENERGY-DELAY, "Leakage, Energy and Speed in Digital Circuits" advanced seminar organized by TIMA Laboratory, Grenoble, France, June 15, 2004.
     


173. 2004 ENERGY MINIMIZATION FOR OPTIMAL ENERGY-DELAY, Infineon, Munich, GERMANY, June 23, 2004.
     


174. 2004 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS, Infineon, Munich, GERMANY, June 23, 2004.
     


175. 2004 DIGITAL CIRCUITS OPTIMIZATION IN ENERGY-DELAY SPACE, Intel Advanced Microprocessor Research Laboratory, Hillsboro, Oregon, December 6, 2004.
     


176. 2005 CLOCKING OF DIGITAL SYSTEMS FOR HIGH-PERFORMANCE AND LOW-POWER, Tutorial Presentation, International Symposium on Circuits and Systems, Kobe, JAPAN, May 23, 2005.
     


177. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, SRC Forum, June 24, 2005.
     


178. 2005 ENERGY-DELAY TRADE-OFF IN CMOS DIGITAL CIRCUITS DESIGN, National Chiao Tung University, Hsinchu, Taiwan, June 30, 2005.
     


179. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, School of Electrical and Computer Engineering, Royal Melbourne Institute of Technology, Melbourne, Victoria, AUSTRALIA, July 8, 2005.
     


180. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, Department of Electrical and Electronic Engineering seminar, The University of Melbourne, Victoria, AUSTRALIA, July 8, 2005.
     


181. 2005 ENERGY-DELAY TRADE-OFF IN CMOS DIGITAL CIRCUITS, School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, AUSTRALIA, July 26, 2005.
     


182. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, Presentation at the meeting of the Swedish Foundation for Strategic Research, Linkoping, SWEDEN, August 25, 2005.
     


183. 2005 LOW POWER DESIGN OF CMOS DIGITAL CIRCUITS, IEEE Solid-State Distinguished Lecture, IEEE-SSC Sweden Chapter, Linkoping University, SWEDEN, August 26, 2005.
     


184. 2005 DIGITAL SYSTEM CLOCKING: HIGH-PERFORMANCE AND LOW-POWER ASPECTS, Invited Tutorial, 8^th EUROMICRO Conference on Digital System Design, Porto, PORTUGAL, August 30, 2005.
     


185. 2005 LOW-POWER DESIGN METHODOLOGY FOR CMOS DIGITAL CIRCUITS: APPLICATION TO STANDARD LIBRARIES, Presentation at UMC, Hsinchu, TAIWAN, September 30, 2005.
     


186. 2005 ENERGY-DELAY TRADE-OFF IN CMOS DIGITAL CIRCUITS DESIGN, Presentation at Dallas IEEE CAS Workshop, Richardson, Texas, October 10, 2005.
     


187. 2005 CLOCK SKEW ABSORBING FLIP-FLOP DESIGN AND DIGITAL TIMING PARTITION, Tutorial Presentation, UMC, Hsinchu, TAIWAN, October 31, 2005.
     


188. 2005 ENERGY-EFFICIENT OPTIMIZATION OF THE VITERBI ACS UNIT ARCHITECTURE, Presentation at the 1^st Asian Solid-State Circuits Conference, Hsinchu, TAIWAN, November 2, 2005.