INDUSTRY

PATENTS

PUBLICATIONS

PRESENTATIONS

2003-on__
2002-____
2000-2001
1996-1999
1994-1995
1990-1993
1982-1989

108. 2000 Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, IBM Austin Research Center, Austin, Texas, February 18, 2000.
     


109. 2000 Advanced Logic Design, Berkeley Summer Institute, University of California, Berkeley, June 7-9, 2000.
     


110. 2000 Design Techniques for LOW POWER, ST Microelectronics, Grenoble, FRANCE, July 31, 2000.
     


111. 2000 clocked timing elements in high-performance and LOW-POWER systems, ST Microelectronics, La Jolla, California, November 6, 2000.
     


112. 2001 VLSI ARITHMETIC, Online Symposium for Electronics Engineers (OSEE), scheduled to be aired, 5pm EST (22pm GMT), January 23, 2001.
     


113. 2001 PROCESSOR DESIGN CHALLENGES, Microprocessor Design Workshop, International Solid-State Circuits Conference, San Francisco, February 8, 2001.
     


114. 2001 CLOCKED TIMING ELEMENTS FOR HIGH-PERFORMANCE AND LOW POWER VLSI SYSTEMS, IBM Sponsored Computer Architecture Seminar Series, University of Texas a Austin, February 12, 2001.
     


115. 2001 COMPUTATIONAL REQUIREMENTS FOR MEDIA SIGNAL PROCESSING, Electrical and Computer Engineering Department, University of Texas at Austin, February 12, 2001.
     


116. 2001 Clocked Storage Elements: Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, Ecole Superieure d' Ingenieurs en Electrotechnique et Electronique, ESIEE, Paris, FRANCE, March 21, 2001.
     


117. 2001 Clocked Storage Elements: Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, Barcelona, SPAIN, March 23, 2001.
     


118. 2001 VLSI ARITHMETIC: ADDERS AND MULTIPLIERS, 29^ème École de Printemps d'Informatique Théorique: Arithmétique des Ordinateurs, Prapoutel-Les-Sept-Laux, FRANCE, March 26, 2001.
     


119. 2001 Clocked Storage Elements: Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, TIMA, Grenoble, FRANCE, March 28, 2001.
     


120. 2001 High-speed VLSI arithmetic units: adders and multipliers, Electrical Engineering Department Colloquia, University of California Los Angeles, May 10, 2001.
     


121. 2001 Timing Elements and Timing issues in High-Performance Processors, Event sponsored by CAS Distinguished Lecturer Program and by IEEE French Section, Institut Supérieur d'Electronique de Paris, Paris, FRANCE, May 29, 2001.
     


122. 2001 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Event sponsored by CAS Distinguished Lecturer Program and by IEEE French Section, Institut Supérieur d'Electronique de Paris, Paris, FRANCE, May 29, 2001.
     


123. 2001 Low-Power Design Techniques in Digital Systems, IEEE Workshop on Low-Power Design, FTFC 2001: Faible Tension Faible Consommation, Paris, FRANCE, May 30 - June 1st, 2001.
     


124. 2001 Will start-ups outperform big COMPANIES?, Panel Presentation, IEEE, 2001 Symposium on VLSI Circuits, Righa Royal Hotel Kyoto, Kyoto, JAPAN, June 14, 2001.
     


125. 2001 Clocked Storage Elements for High-Performance Applications, Fujitsu Laboratories, Kawasaki, Tokyo, JAPAN, June 18, 2001.
     


126. 2001 Clocked Storage Elements for High-Performance and Low-Power SystemS, Invited Tutorial given at the International Conference on Computer Design, ICCD 2001, Austin, Texas, September 24, 2001.