INDUSTRY

PATENTS

PUBLICATIONS

PRESENTATIONS

1. D. T. Ling, V. G. Oklobdzija, N. Raver, "Consistent Precharge Circuit for Cascode Voltage Switch Logic" US Patent No. 4,700,086, Issued: 10/13/1987
   


2. V. G. Oklobdzija, "Register Selection Mechanism and Organization of an Instruction Prefetch Buffer" US Patent No. 4,847,759, Issued: 07/11/1989
   


3. V. G. Oklobdzija, D. T. Ling, "Instruction Prefetch Buffer Control" US Patent No. 4,714,994, Issued: 12/22/1989
   


4. J. Cocke, G. F. Grohoski, V. G. Oklobdzija, "Instruction Control Mechanism for a Computing System with Register Renaming and Queues Indicating Available Registers" US Patent No. 4,992,938, Issued: 02/12/1991
   


5. R. G. Fleck, R. D. Arnold, B. Holmer, V. G. Oklobdzija, E. Chesters "Data Processing Unit With Hardware Assisted Contex Switching Capability" US Patent No. 6,128,641, Issued: 10/03/2000
   


6. V. Stojanovic, V. G. Oklobdzija, "FLIP-FLOP" US Patent No. 6,232,810, Issued: 05/15/2001
   


7. A. A. Farooqui, V. G. Oklobdzija, F. Chehrazi, Wei-Jen Li, A. W. Yu, "Partitioned Shift Right Logic with Rounding Support" US Patent No. 6,243,728, Issued: 06/05/2001
   


8. F. Chehrazi, V. G. Oklobdzija, "High Performance pipelined Data path for a media processor" US Patent No. 6,282,556, Issued: 08/28/2001



9. F. Chehrazi, V. G. Oklobdzija, A. A. Farooqui, "Multiplier Circuit Having an Optimized Booth Encoder / Selector" US Patent No. 6,301,599, Issued: 10/09/2001
   


10. F. Chehrazi, V. G. Oklobdzija, A. A. Farooqui, "High Performance Universal Multiplier" US Patent No. 6,353,843, Issued: 03/05/2002
    


11. B. Nikolic, L. Fu, M. Leung, V. G. Oklobdzija and R. Yamasaki, "Method For Reduced-Complexity Sequence Detection In EEPR4 Magnetic Recording Channel" US Patent No. 6,553,541, Issued: 04/05/2003
    


12. N. Nedovic, V. G. Oklobdzija, W. W. Walker, "Method And System For Reducing Hazards In A Flip-Flop" US Patent No. 6,646,487, Issued: 11/11/2003
    


13. N. Nedovic, V. G. Oklobdzija, W. W. Walker, "Method And System For Improving Speed In A Flip-Flop" US Patent No. 6,693,459, Issued: 02/17/2004
    


14. V. G. Oklobdzija, W. W. Walker, N. Nedovic, "System For Symmetric Pulse Generator Flip-Flop" US Patent No. 6,753,715, Issued: 06/22/2004
    


15. B. Nikolic, L. Fu, M. Leung, V. G. Oklobdzija, R. Yamasaki, "Reduced-complexity sequence detection" European Patent No. EP1058394 (US19990129149P 19990414)
    


16. J. Cocke, G. F. Grohoski, V. G. Oklobdzija, "Register Renaming Device" Japanese Patent No. JP1017126, Issued: 01/20/1989
    


17. R. Fleck, R. Arnold, B. Holmer, V.G. Oklobdzija, E. Chesters, "Data Processing Unit With Hardware Assisted Context Switching Capability" European Patent No. EP1012715, Issued: 06/28/2000
    


18. M. Leung, L. Fu, B. Nikolic, V. G. Oklobdzija, R. Yamasaki, "Method For Simplified Viterbi Detection For Sequence Detection And Viterbi Detector" Japanese Patent No. JP2001053622, Issued: 02/23/2001
    

1. New Configuration of CMOS-Domino Logic, IBM Technical Disclosure Bulletin, YO885-0085, Vol. 30, No. 1, June 1987.
   


2. Switching Circuits Test Generation, IBM Technical Disclosure Bulletin, YO883-0876, Vol. 28, No. 2, July 1985.
   


3. A Method for Fast Carry-Propagation for VLSI Implementations of Addition, IBM Technical Disclosure Bulletin, YO883-0225, Vol. 28, No. 4, September 1985.
   


4. A New Scheme for VLSI Implementation of Fast ALU , IBM Technical Disclosure Bulletin, YO884-0064, Vol. 28, No. 3, August 1985.
   


5. A New Multilevel Scheme for Fast Carry-Skip Addition, IBM Technical Disclosure Bulletin, YO884-0186, Vol. 27, No. 11, April 1985.
   


6. Single Clock CMOS Latch Compatible with Level Sensitive Scan Design, IBM Technical Disclosure Bulletin, Vol. 31, No. 9, February 1989.